Waveshare ESP32-S3 Zero: high-resolution, datasheet, pinout, and specs

Renzo Mischianti

9 hours ago

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The ESP32-S3 Zero is a compact castellated module from Waveshare, powered by the dual-core Xtensa® 32-bit LX7 processor (up to 240 MHz) and integrating Wi-Fi (802.11 b/g/n) and Bluetooth 5.0 (LE). With 4 MB of onboard flash, 2 MB of PSRAM, and hardware crypto accelerators, it’s ideal for space-constrained IoT, wearable, and mobile applications

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PINs

GPIO33 to GPIO37 pins are not exposed; these pins are used for Octal PSRAM.
GPIO21 to connected with WS2812 RGB LED.
ESP32-S3-Zero does not employ a USB to UART chip. When flashing firmware, press and hold the BOOT button (GPIO0) and then connect the Type-C cable.
The “TX” and “RX” markings on the board indicate the default UART0 pins for ESP32-S3-Zero. Specifically, TX is GPIO43, and RX is GPIO44.

Specifications

Feature	Details
SoC	ESP32-FH4R2 (Xtensa LX7 dual-core @ up to 240 MHz)
Wireless	2.4 GHz Wi-Fi (b/g/n), Bluetooth 5.0 (LE)
Memory	4 MB Flash, 2 MB PSRAM; 512 KB SRAM, 384 KB ROM
GPIO	24 programmable pins (19 exposed; GPIO33–37 for PSRAM)
USB	Type-C full-speed controller (no external UART chip)
Power Input	5 V castellated hole (3.7–6 V input); onboard 3.3 V regulator
Onboard LED	WS2812 RGB connected to GPIO21
Secure Boot & Crypto	AES, RSA, SHA, HMAC, RNG
Dimensions	18 mm × 23.5 mm (pitch 2.54 mm between castellated rows)

CPU and Memory

Xtensa® dual-core 32-bit LX7 microprocessor,
up to 240 MHz
CoreMark® score:
– 1 core at 240 MHz: 613.86 CoreMark; 2.56 CoreMark/MHz
– 2 cores at 240 MHz: 1181.60 CoreMark; 4.92 CoreMark/MHz
128-bit data bus and SIMD commands
384 KB ROM
512 KB SRAM
16 KB SRAM in RTC
SPI, Dual SPI, Quad SPI, Octal SPI, QPI and OPI interfaces that allow connection to multiple flash and external RAM
Flash controller with cache is supported
Flash in-Circuit Programming (ICP) is supported

Advanced Peripheral Interfaces

45 × programmable GPIOs
Digital interfaces:
– 4 × SPI
– 1 × LCD interface (8-bit ~16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411
– 1 × DVP 8-bit ~16-bit camera interface
– 3 × UART
– 2 × I2C
– 2 × I2S
– 1 × RMT (TX/RX)
– 1 × pulse counter
– LED PWM controller, up to 8 channels
– 1 × full-speed USB OTG
– 1 × USB Serial/JTAG controller
– 2 × MCPWM
– 1 × SDIO host controller with 2 slots
– General DMA controller (GDMA), with 5 transmit channels and 5 receive channels Espressif Systems 3
Submit Documentation Feedback ESP32-S3 Series Datasheet v1.6
– 1 × TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0)
Analog interfaces:
– 2 × 12-bit SAR ADCs, up to 20 channels
– 1 × temperature sensor
– 14 × touch sensing IOs Timers:
– 4 × 54-bit general-purpose timers
– 1 × 52-bit system timer
– 3 × watchdog timers

Wi-Fi

IEEE 802.11 b/g/n-compliant
Supports 20 MHz, 40 MHz bandwidth in 2.4 GHz band
1T1R mode with data rate up to 150 Mbps
Wi-Fi Multimedia (WMM)
TX/RX A-MPDU, TX/RX A-MSDU
Immediate Block ACK
Fragmentation and defragmentation
Automatic Beacon monitoring (hardware TSF)
4 × virtual Wi-Fi interfaces
Simultaneous support for Infrastructure BSS in Station, SoftAP, or Station + SoftAP modes Note that when ESP32-S3 scans in Station mode, the SoftAP channel will change along with the Station channel
Antenna diversity
802.11mc FTM

Bluetooth

Bluetooth LE: Bluetooth 5, Bluetooth mesh
High power mode (20 dBm)
Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps
Advertising extensions
Multiple advertisement sets
Channel selection algorithm #2
Internal co-existence mechanism between Wi-Fi and Bluetooth to share the same antenna

Low Power Management

Power Management Unit with five power modes
Ultra-Low-Power (ULP) coprocessors:
– ULP-RISC-V coprocessor
– ULP-FSM coprocessor

Security

Secure boot
Flash encryption
4-Kbit OTP, up to 1792 bits for users
Cryptographic hardware acceleration:
– AES-128/256 (FIPS PUB 197)
– Hash (FIPS PUB 180-4)
– RSA
– Random Number Generator (RNG)
– HMAC
– Digital signature